View ZL30110_6132555.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2006, zarlink semiconductor inc. all rights reserved. features ? synchronizes to 8 khz, 2.048 mhz, 8.192 mhz or 16.384 mhz ? provides a range of output clocks: ? 65.536 mhz tdm clock locked to the input reference ? general purpose 25 mhz fan-out to 6 outputs locked to the external crystal or oscillator ? general purpose 125 mhz and 66 mhz or 100 mhz locked to the external crystal or oscillator ? provides dpll lock and reference fail indication ? automatic free run mode on reference fail ? dpll bandwidth of 922 hz for all rates of input reference and 58 hz for an 8 khz input reference ? less than 5 psec rms on 25 mhz outputs, and less than 0.6 ns pp intrinsic jitter on the all other outputs ? minimal input to output and output to output skew ? 25 mhz external master clock source: clock oscillator or crystal ? simple hardware control interface applications ? clock rate conversion pll for telecommunication equipment ? small/medium enterprise router / gateway ? broadband access (xpon/xdsl) cpe gateway description the ZL30110 clock rate conversion digital phase- locked loop (dpll) provides accurate and reliable frequency conversion. the ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. in the locked mode, the reference input is continuously monitored for a failure condition. in the event of a failure, the dpll continues to provide a stable free running clock ensuring system reliability. november 2006 ordering information ZL30110lde 32 pin qfn tubes bake & dry pack ZL30110lde1 32 pin qfn* tubes bake & dry pack *pb free matte tin -40 c to +85 c ZL30110 telecom rate conversion dpll data sheet figure 1 - functional block diagram rst osco osci ref lock apll c65o ref_fail c100/66o dpll 6 x c25o apll c125o out_sel state machine reference master clock frequency synthesizer select mux monitor
ZL30110 data sheet 2 zarlink semiconductor inc. 1.0 physical description 1.1 pin connections figure 2 - pin connections (32 pin 5 mm x 5 mm qfn with e-pad) ZL30110 26 28 30 32 12 10 8 6 4 2 14 16 18 22 24 20 gnd (33- e-pad) c25co c25do c25eo av dd c25fo c65o av dd av core v core lock ref_fail gnd gndv core v core gnd c125o c100/66o v dd out_sel v dd osci osco rst c25bo c25ao gnd ref ic v dd gnd ic
ZL30110 data sheet table of contents 3 zarlink semiconductor inc. 1.0 physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 reference monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 digital phase lock loop (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 frequency synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 apll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 dpll modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 freerun mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.0 measures of performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 jitter generation (int rinsic jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.1 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ZL30110 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections (32 pin 5 mm x 5 mm qfn with e-pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - reference monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4 - dpll mode switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5 - clock oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6 - power-up reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8 - input to output timing for synchronous clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9 - asynchronous clocks input to output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ZL30110 data sheet list of tables 5 zarlink semiconductor inc. table 1 - clock oscillator specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2 - crystal oscillator specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ZL30110 data sheet 6 zarlink semiconductor inc. 1.2 pin description pin # name i/o type description input reference 28 ref i reference (lvcmos, schmitt trigger). this is the input reference source used for synchronization. one of four possible frequencies may be used: 8 khz, 2.048 mhz, 8.192 mhz or 16.384 mhz. this pin is internally pulled down to gnd. master clock 11 osci i oscillator master clock (input). for crystal operation, a 25 mhz crystal is connected from this pin to osco. for cl ock oscillator operation, this pin must be connected to a clock source. 10 osco o oscillator master clock (lvcmos). for crystal operation, a 25 mhz crystal is connected from this pin to osci. this output is not suitable for driving other devices (see c25o output pin for support of such function). fo r clock oscillator operation, this pin must be left unconnected. control and status 9rst i reset (lvcmos, schmitt trigger). a logic low at this input resets the device. on power up, the rst pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. when the rst pin goes high, the device will transition into a reset state for 3 ms. in the reset state all outputs will be forced into high impedance. 13 out_sel i output select (lvcmos, schmitt trigger). this input pin selects the output clock frequency of the c100/66o, a logic low selects the 100 mhz output, while logic high selects the 66 mhz output clock. 3 ref_fail o reference failure indicator (lvcmos). a logic high at this pin indicates that the ref reference frequency is exhibiting abrupt phase or frequency change. 2locko lock indicator (lvcmos). this output goes to a logic high when the pll is frequency locked to a valid input reference. output clocks 19 c65o o clock 65.536 mhz (lvcmos). this output is used in general tdm applications. the falling edge of this clock is aligned with rising edge of the input reference (ref). 26 c25ao o clock 25 mhz (lvcmos). this is a buffered external oscillator clock, the phase and frequency accuracy of this output trac ks that of the external crystal or oscillator. 25 c25bo o clock 25 mhz (lvcmos). this is a buffered external oscillator clock, the phase and frequency accuracy of this output trac ks that of the external crystal or oscillator. 24 c25co o clock 25 mhz (lvcmos). this is a buffered external oscillator clock, the phase and frequency accuracy of this output trac ks that of the external crystal or oscillator. 23 c25do o clock 25 mhz (lvcmos). this is a buffered external oscillator clock, the phase and frequency accuracy of this output trac ks that of the external crystal or oscillator.
ZL30110 data sheet 7 zarlink semiconductor inc. 22 c25eo o clock 25 mhz (lvcmos). this is a buffered external oscillator clock, the phase and frequency accuracy of this output trac ks that of the external crystal or oscillator. 20 c25fo o clock 25 mhz (lvcmos). this is a buffered external oscillator clock, the phase and frequency accuracy of this output trac ks that of the external crystal or oscillator. 15 c100/66o o clock 100 mhz or 66 mhz (lvcmos). this is 100 mhz or 66 mhz rate converted clocks off the 25 mhz fixed frequency external oscillator, the phase and frequency accuracy of this output trac ks that of the external crystal or oscillator device. 16 c125o o clock 125 mhz (lvcmos). this is 125 mhz rate converted clock off the 25 mhz fixed frequency exter nal oscillator, the phase and frequency accuracy of this output tracks that of the ex ternal crystal or oscillator device. miscellaneous 29 ic internal connection. connect to vdd. 32 ic internal connection. connect to vdd. power and ground 12 v dd positive supply voltage. +3.3 v dc nominal. 14 v dd positive supply voltage. +3.3 v dc nominal. 30 v dd positive supply voltage. +3.3 v dc nominal. 1v core positive supply voltage. +1.8 v dc nominal. 6v core positive supply voltage. +1.8 v dc nominal. 7v core positive supply voltage. +1.8 v dc nominal. 17 av core positive analog supply voltage. +1.8 v dc nominal. 18 av dd positive analog supply voltage. +3.3 v dc nominal. 21 av dd positive analog supply voltage. +3.3 v dc nominal. 4gnd ground. 0v. 5gnd ground. 0v. 8gnd ground. 0v. 27 gnd ground. 0v. 31 gnd ground. 0v. 33 e-pad gnd internal connection. package e-pad, this pin is internally connected to device gnd, it should be connected to gnd. pin # name i/o type description
ZL30110 data sheet 8 zarlink semiconductor inc. 2.0 functional description 2.1 reference monitor the input reference is monitored by two reference monito r blocks. the block diagram of reference monitoring is shown in figure 3. the reference frequency is detecte d and the clock is conti nuously monitored for two independent criteria that indi cate abnormal behavior of the reference signal, for example; loss of clock or excessive level of frequency error. to ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. ? reference frequency detector (rfd) : this detector determines whether the frequency of the reference clock is 8 khz, 2.048 mhz, 8.192 mhz or 16.384 mhz and provides this information to the various monitor circuits and the phase detector circuit of the dpll. ? coarse frequency monitor (cfm) : this circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. ? single cycle monitor (scm) : this detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. figure 3 - reference monitor circuit exceeding the thresholds of any of the monitors forces the corresponding ref_fail pin to go high. the single cycle and coarse frequency failure flags force the dpll into freerun mode. reference frequency detector single cycle monitor coarse frequency monitor ref or mode select state machine dpll in freerun mode ref_fail
ZL30110 data sheet 9 zarlink semiconductor inc. 2.2 digital phase lock loop (dpll) the dpll of the ZL30110 consists of a phase detector, a loop filter and a digitally controlled oscillator. phase detector - the phase detector compares the input refe rence signal to the feedbac k signal and provides an error signal corresponding to the phase difference between the two. loop filter - the loop filter is simi lar to a first order low pass filter with a bandwidth of 922 hz. for stability reasons, the loop filter bandwidth for an 8 khz reference is limited to a maximum of 58 hz. digitally controlled oscillator (dco) - the dco receives the filtered signal from the loop filter, and based on its value, generates a corresponding digita l output signal. the synchronization method of the dco is dependent on the state of the ZL30110. in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in freerun mode, the dco is free running with an accu racy equal to the accuracy of the osci 25 mhz source. lock indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock- window for a certain time. the select ed phase-lock-window guarantees the stabl e operation of the lock pin with maximum network jitter and wander on the reference input. if the dpll goes into freerun mode, the lock pin will initially stay high for 0.1 s. if at that point the dpll is still in freerun mode, the lock pin will go low. in freerun mode the lock pin will go low immediately. 2.3 frequency synthesizers the output of the dco is used by the frequency synthesiz er to generate the output clock which is synchronized to the inputs (ref). the frequency synthesizer uses digital techniques to generate output clock and advanced noise shaping techniques to minimize the output jitter. the cl ock and frame pulse outputs ha ve limited driving capability and should be buffered when driving high capacitance loads. 2.4 state machine as shown in figure 1, the stat e machine controls the dpll. 2.5 apll the ZL30110 employ two analog plls as a clock multiplying and rate conversion engine. one apll is used to multiply the master clock (osci) to 125 mhz, a sec ond apll is used to convert the master clock (osci) to 100 mhz or 66 mhz clock. 2.6 master clock the ZL30110 can use either a clock or crystal as the master timing source. for recommended master timing circuits, see the applications - master clock section.
ZL30110 data sheet 10 zarlink semiconductor inc. 3.0 dpll modes of operation the ZL30110 has two possible modes of operation; normal, and freerun. the ZL30110 starts up in freerun mode, it automatically transitions to normal mode if a valid refe rence is available and transitions to freerun mode if the reference fails. 3.1 freerun mode freerun mode is typically used when an independent clock source is required or im mediately following system power-up before synchronization is achieved. in freerun mode, the ZL30110 provid es timing and synchronization signals which are based on the master clock frequency (supplied to osci pin) only and are not synchronized to the reference input signals. the accuracy of the output clock is equal to t he accuracy of the master clock (osci). so if a 32 ppm output clock is required, the master clock must also be 32 ppm. see applications - section 5.2, ?master clock?. freerun mode is also used for short durations while syst em synchronization is tempor arily disrupted. the accuracy of the output clock during these input reference disruptions is be tter than the accuracy of the master clock (osci), but it is off compared to t he reference before disruptions. 3.2 normal mode normal mode is typically used when a system clock sour ce, synchronized to the network is required. in normal mode, the ZL30110 provides timing sync hronization signals, which are synchr onized to the input (ref). the input reference signal may have a nominal frequency of 8 k hz, 2.048 mhz, 8.192 mhz or 16.384 mhz. the frequency of the reference inputs are automatically detected by the reference monitors. when the ZL30110 comes out of reset it will initially go into freerun mode and generate a clock with the accuracy of its freerunning local oscillator (see fi gure 4). if the ZL30110 determines t hat its selected reference is disrupted (see figure 3), it will remain in freerun until the selected reference is no longer disrupted. if the ZL30110 determines that the reference is not di srupted (see figure 3) then the state ma chine will cause the dpll to recover from freerun and transition to normal mode. when the ZL30110 is operating in normal mode, if it determines that the input reference is disrupted (figure 3) then its state machine will cause it to automatically go to freerun mode. when the ZL30110 determines that its selected reference is not disrupted then the state machine will cause the dpll to recover fr om freerun and transition to normal mode. figure 4 - dpll mode switching freerun ref_fail=0 ref_fail=1 rst normal
ZL30110 data sheet 11 zarlink semiconductor inc. 4.0 measures of performance the following are some pll performance indi cators and their corresponding definitions. 4.1 jitter timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. wander is defined as the low-frequency variation of the clock e dges from their ideal positions in time. high and low frequency variation imply phase oscillation frequencies re lative to some demarcation frequency. (often 10 hz or 20 hz for ds1 or e1, higher for sonet/sdh clocks.) jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 4.2 jitter generation (intrinsic jitter) jitter generation is the measure of the jitter produced by the pll and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the device, and measuri ng its output jitter. jitter is usually measured with various band limiting filt ers depending on the applicable standards. 4.3 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. 4.4 lock time this is the time it takes the pll to frequency lock to t he input signal. phase lock occurs when the input signal and output signal are aligned in phase with respect to each othe r within a certain phase distance (not including jitter). lock time is affected by many factors which include: ? initial input to output phase difference ? initial input to output frequency difference ? pll loop filter bandwidth the presence of input jitter makes it difficult to define when the pll is locked as it may not be able to align its output to the input within the required phase distance, dependen t on the pll bandwidth and the input jitter amplitude and frequency.
ZL30110 data sheet 12 zarlink semiconductor inc. 5.0 applications this section contains ZL30110 application specific details for power supply decoupling, reset operation, clock and crystal operation. 5.1 power supply decoupling jitter levels on the ZL30110 output clocks may increase if the device is exposed to excessive noise on its power pins. for optimal jitter performance, the ZL30110 device s hould be isolated from noise on power planes connected to its 3.3 v and 1.8 v supply pins. for recommended common layout practices, refer to zarlink application note zlan-178. 5.2 master clock the ZL30110 can use either a clock or crystal as the master timing source. 5.2.1 clock oscillator when selecting a clock oscillator, numerous parameters must be considered. this includes absolute frequency, frequency change over temperature, output rise and fa ll times, output levels, duty cycle and phase noise. the output clock should be connected directly (not ac coupled) to the osci input of the ZL30110, and the osco output should be left open as shown in figure 5. figure 5 - clock os cillator circuit 1 frequency 25 mhz 2 tolerance as required (better than +/-50ppm) 3 rise & fall time < 8 ns 4 duty cycle 40% to 60% table 1 - clock oscillator specification +3.3 v 25 mhz out gnd 0.1 f +3.3 v osco ZL30110 osci no connection
ZL30110 data sheet 13 zarlink semiconductor inc. 5.2.2 crystal oscillator alternatively, a crystal oscilla tor may be used. the a ccuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. typically, for a 25 mhz crystal specified with a 32 pf load capacitance, each 1 pf change in load capacitance contributes appro ximately 9 ppm to the frequency deviation. consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. the crystal should be a fundamental mode type - not an over tone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. a typical crystal oscillator specification is shown in table 2. . 1 frequency 25 mhz 2 tolerance as required (better than +/-50ppm) 3 oscillation mode fundamental 4 resonance mode parallel 5 load capacitance as required 6 maximum series resistance 50 ? table 2 - crystal oscillator specification
ZL30110 data sheet 14 zarlink semiconductor inc. 5.3 power up sequence the ZL30110 requires that the 3. 3 v supply is not powered up after the 1.8 v supply. this is to prevent the risk of latch-up due to the presence of protection diodes in the io pads. two options are given: 1. power-up the 3.3 v supply fully first, then power up the 1.8 v supply 2. power up the 3.3 v supply and the 1.8 v supply simultan eously, ensuring that the 3.3 v supply is never lower than a few hundred millivolts below the 1.8 v supply (e.g., by using a schottky diode or controlled slew rate) 5.4 reset circuit a simple power up reset circuit with about a 60 s reset low time is shown in figure 6. resistor r p is for protection only and limits current into the rst pin during power down conditions. the re set low time is not critical but should be greater than 300 ns. figure 6 - power-up reset circuit +3.3 v rst r p 1 k ? c 10 nf r 10 k ? ZL30110
ZL30110 data sheet 15 zarlink semiconductor inc. 6.0 characteristics 6.1 ac and dc electr ical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated. * voltages are with respect to ground (gnd) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v dd_r -0.5 4.6 v 2 core supply voltage v core_r -0.5 2.5 v 3 voltage on any digital pin v pin -0.5 6 v 4 voltage on osci and osco pin v osc -0.3 v dd + 0.3 v 5 current on any pin i pin 30 ma 6 storage temperature t st -55 125 c 7esd rating v esd 2k v recommended operating conditions* characteristics sym. min. typ. max. units 1 supply voltage v dd 3.1 3.3 3.5 v 2 core supply voltage v core 1.7 1.8 1.9 v 3 operating temperature t a -40 25 85 c 4 input voltage v i 03.33.5 v dc electrical characteristics* characteristics sym. min. max. units notes 1 supply current i dd 115 ma all outputs loaded with 30 pf 2 core supply current i core 20 ma all outputs loaded with 30 pf 3 schmitt trigger low to high threshold point v cih 1.43 1.85 v 4 schmitt trigger high to low threshold point v cil 0.8 1.1 v 5 input leakage current i il -105 105 a v i =v dd or 0 v
ZL30110 data sheet 16 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. figure 7 - timing parameter measurement voltage levels 6 high-level output voltage v oh 2.4 v i oh = 8 ma for clock outputs, 4ma for status outputs 7 low-level output voltage v ol 0.4 v i ol = 8 ma for clock outputs, 4ma for status outputs ac electrical charact eristics* - timing parameter measuremen t voltage levels (see figure 7). characteristics sym. cmos units 1 threshold voltage v t 0.5xv dd v 2 rise and fall threshold voltage high v hm 0.7xv dd v 3 rise and fall threshold voltage low v lm 0.3xv dd v dc electrical characteristics* characteristics sym. min. max. units notes t irf, t orf timing reference points all signals v hm v t v lm t irf, t orf
ZL30110 data sheet 17 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * period min/max values are the limits to avoid a single-cycle fault detection. short-term and long-term average periods must b e within +/-130 ppm limit. * supply voltage and operating temperature are as per recommended operating conditions. outputs loaded with 30 pf. figure 8 - input to output timing for synchronous clock ac electrical characteristi cs* - timing for input re ference (see figure 8). characteristics symbol min. typ. max. units 1 8 khz reference period t ref8kp 120 125 128 s 2 2.048 mhz reference period t ref2p 263 488 712 ns 3 8.192 mhz reference period t ref8p 63 122 175 ns 4 16.384 mhz reference period t ref16p 38 61 75 ns 5 reference pulse width high or low t refw 15 ns ac electrical characteris tics* - input to output timing fo r synchronous clock (see figure 8). characteristics symbol min. max. units 1 8 khz reference input to c65o delay t ref8_c65d -0.7 6.7 ns 2 2.048 mhz reference input to c65o delay t ref2_c65d 1.5 9.6 ns 3 8.192 mhz reference input to c65o delay t ref8_c65d 2.1 9.2 ns 4 16.384 mhz reference input to c65o delay t ref16_c65d 2.1 9.6 ns 5 c65o pulse width low t c65l 7.0 8.6 ns 6 output clock rise or fall time t orf 1.1 2.3 ns ref t refp t refw t refw c65o t ref_c65d t c65l
ZL30110 data sheet 18 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. figure 9 - asynchronous clocks input to output timing * supply voltage and operating temperature are as per recommended operating conditions. ** buffered osci clock input, characterization data did not account for input clock duty cycle nor rise/fall time degradation. 6.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions. ac electrical characteristics* - i nput to output timing for asyn chronous clocks (see figure 9). characteristics symbol min. max. units notes 1 25 mhz master clock inpu t to c25a/b/c/d/e/fo delay t m_c25d 314ns ac electrical characteristics* - output timing for asynchronous clocks (see figure 9). characteristics symbol min. max. units notes 1 c25a/b/c/d/e/fo pulse width low ** t c25l 18 22 ns 30 pf output load 2 c125o pulse width low t c125l 3.2 4.6 ns 25 pf output load 3 c100o pulse width low t c100l 4.1 5.6 ns 30 pf output load 4 c66o pulse width low t c66l 6.8 8.0 ns 30 pf output load performance characteristics* - functional characteristics min. typ. max. units notes 1 dpll capture range -130 +130 ppm the 25 mhz master clock oscillator set at 0.ppm lock time 2 dpll 58 hz filter 1 s input reference = 8 khz, 100 ppm frequency offset 3 dpll 922 hz filter 1 s input reference 8khz, 100 ppm frequency offset 4 apll 450 khz filter 150 s master clock t m_c25d asynchronous output clocks 25mhz
ZL30110 data sheet 19 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics* - unfilt ered jitter generation - pk-pk characteristics max. [ns pp ] notes 1 c65o (65.536 mhz) 0.60 3 c25a/b/c/d/e/fo (25 mhz) 0.20 4 c125o (125 mhz) 0.54 5 c100o (100 mhz) 0.60 6 c66o (66 mhz) 0.60 performance characteris tics* - filtered jitter generation - rms characteristics max. [ps rms ] notes 1 c25a/b/c/d/e/fo (25 mhz) - (625 khz - nyquist) 4 2 c125o (125 mhz) (625 khz - nyquist) 20
c zarlink semiconductor 2003 all rights reserved. issue apprd. date acn 30-01-2004 1 package code previous package codes 15-08-2005 cdca 2 cdca 3 cdca 22-08-2005
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of ZL30110

	To Download ZL30110 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .